ASIC Verification using System Verilog (SV) + Project Demo
Verification in ASIC Flow, System Verilog Language constructs, use of SV in verification, Testbench and Tests
ASIC Verification using System Verilog (SV) + Project Demo free download
Verification in ASIC Flow, System Verilog Language constructs, use of SV in verification, Testbench and Tests
System Verilog course content is designed for beginners to experts ;
The modules can be learnt and practiced in couple of weeks:
The detailed course syllabus is as follows: It is split into 2 parts
Section I:
Session 01 • ASIC flow-Design verification and Verilog Refresh
Lab 1 - Verilog Testbench development
Session 02 •System Verilog Introduction, Data Types
Lab 2 - Programs with Various data types
Session 03 •Operators-Control Statements-loops
Lab 3- SV Constructs practice
Session 04 •Arrays, Queues
Lab 4 - Arrays, Queues Constructs practice
Session 05 •OOPs-Classes-Objects
Section II:
Session 06 •Randomization and Constraints
Lab 6- Randomization
Session 07 •Inter process Communication
Lab 7- Use of mail box, Semaphores and Queues
Session 08 •Interfaces
Lab 8-Use of interfaces, mod port, clocking block
Session 09 • Testbench development
Lab 09- Use of SV constructs for driver/BFM
Session 10 •Code and Functional Coverage
Lab 10-Simulate an example for coverage
Various example codes are explained in the course. Few of the programs are simulated in the industry standard simulators.
A protocol example is also taken and testbench code is developed and test cases are written for the project.
The assignment given helps to practice the code writing and further using for test bench and testcase development
