ASIC Design Verification using SV-UVM + Project Demo
UVM Testbench development, Test case development, An example Project, simulation using industry standard simulator
ASIC Design Verification using SV-UVM + Project Demo free download
UVM Testbench development, Test case development, An example Project, simulation using industry standard simulator
This course covers the topics, basics of UVM methodology, components, Objects, UVM Factory, configuration, phases, Reports. Step wise approach to build testbench using driver, sequencer, agent, environment, test and top test bench. Building sequences for verifying the features of an example IP. Outcome of this course, one can develop UVM testbench and testcases right from the scratch. The course is also covering an example test bench creation and explains how to write testcases. How to simulate. This is demonstrated with one simulator.
This course is useful for Students, who are studying BE/BTech/MTech in Electronics and communication and want to learn UVM, do internship. Also those who have completed Engineering , can opt for this course and learn UVM, simulate with free tools available in edaplayground.
This is a complete course with project demonstration and contains the assignments to make the UVM learning easy. The agenda is as follows:
Session 01 - UVM Overview
Session 02 - UVM Components and Objects
Session 03 - TLM
Session 04 - UVM Factory
Session 05 - UVM Configuration
Session 06 - UVM Phases
Session 07-1 - UVM Report
Session 07-2 - UVM Report Example
Session 08 - UVM Sequencer, Driver
Session 09 - UVM Agent, Monitor
Session 10 - UVM Test, Scoreboard
Session 11 - UVM Topology
Session 12-1 - Test sequences part 1
Session 12-2 - Test sequences part 2
Assignments
Once you go through the course, you can apply and get job in semiconductor companies as design verification engineer.
